| abstract |
An electronic component (600, 700) comprising: a first chip carrier (110a, 110b); a second chip carrier (120a, 120b) isolated from the first chip carrier (110); wherein the first and second chip carriers each comprise a double layer structure comprising a first chip carrier a first power semiconductor chip (111) mounted on and electrically connected to the upper layer of the double-layered structure of the first chip carrier (110); a second power semiconductor chip (121); mounted and electrically connected to the upper layer of the double layer structure of the second chip carrier (120); an electrically insulating material (150) at least partially covering the first power semiconductor chip (111) and the second power semiconductor chip (121) and the electrically conductive via lines surrounds; and an electrical connection (131) electrically connecting the first power semiconductor chip (111) to the second power semiconductor chip (121), the electrical connection (131) comprising a contact terminal, a deposited conductor or an electrically conductive bonding wire. |