| Predicate |
Object |
| assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_36333273e27f0db23ddddbf80ba79ba7 |
| classificationCPCAdditional |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-165
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-267
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2924-13067 |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-10
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-41791
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-66795
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-7831
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-7842
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-7849
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-26506
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-7855
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-06
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-7843
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-7848
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-7851
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-785
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-306
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-7847
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-1033 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-78
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-336 |
| filingDate |
2015-06-02^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_26c7430865a6bab90b34b20a1839c1de
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_8941b9fa39b55eefcb54dc8b3e875a60 |
| publicationDate |
2016-07-21^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
DE-102015108690-A1 |
| titleOfInvention |
SEMICONDUCTOR DEVICE CONTAINING FRAMEWORK AND MANUFACTURING METHOD |
| abstract |
A semiconductor FinFET device includes a ridge structure disposed over a substrate. The ridge structure comprises a channel layer. The FinFET device also includes a gate structure that includes a gate electrode layer and a gate dielectric layer that cover a portion of the fin structure. Sidewall insulating layers are disposed over both major sides of the gate electrode layer. The FinFET device includes a source and a drain, each including a stressor layer disposed in a recess formed by removing the fin structure that is not covered by the gate structure. The stressor layer includes first to third stressor layers that are formed in this order. At the source, an interface between the first stressor layer and the channel layer is under one of the sidewall insulating layers closer to the source or gate electrode. |
| priorityDate |
2015-01-15^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |