| abstract |
Peripheral unit controller in a data processing system. The peripheral unit controller consists of two sub-processors (100a, 100d) with paired outputs. In addition, each duplicate sub-processor consists of a pair of microprocessors (300, 307) also having paired outputs. The synchronization path allows each microprocessor (300, 307) to execute these diagnostics independently, to synchronize with the other microprocessor of the pair. After synchronization takes place in the two microprocessors in each of the sub-processors, the sub-processors are synchronized. Synchronization is achieved using a real time clock and the interrupt structure of each microprocessor. |