http://rdf.ncbi.nlm.nih.gov/pubchem/patent/EP-0164138-A1

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filingDate 1981-02-11^^<http://www.w3.org/2001/XMLSchema#date>
inventor http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_c892a2e307111f7ee7a0809acda9e6bd
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publicationDate 1985-12-11^^<http://www.w3.org/2001/XMLSchema#date>
publicationNumber EP-0164138-A1
titleOfInvention Data processing system with a plurality of input/output buses
abstract A CPU (10) communicates with various devices on a system bus (11) and communicates with two further groups of devices by way of interfaces (14) and (14A) and corresponding buses (15B) and (15A) whose timing and control characteristics are different from each other and from those of the system bus (11). The interface (14) polls the device which may be on its bus (15B) and keeps a record of the devices actually present. When access to a device is required, the interface (14) provides access via its bus (15B) if the device is recorded as present on that bus. Otherwise it provides a signal to the interface (14a) to enable access via the corresponding bus (15A).
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http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-5276814-A
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-8015326-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-5655112-A
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-5199106-A
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/EP-0260392-A2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/EP-0594024-A1
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/EP-0260392-A3
priorityDate 1980-02-11^^<http://www.w3.org/2001/XMLSchema#date>
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