| abstract |
The latch circuit includes at least three gate circuits (3, 1, 2), and a noise resistance circuit (8). A first gate circuit (3) receives a data signal (DT) and a clock signal (CLK). A second gate circuit (1) is operatively connected to an output of the first gate circuit (3). A third gate circuit (2) receives an inverted clock signal ( CLK ) at an input terminal, is operatively connected to an output of the second gate circuit (1) at another input terminal, and is operatively connected to another input terminal of the second gate circuit (1), at an output terminal, so that a feedback line is formed between the second and third gate circuits (1, 2). The noise resistance circuit (8) has at least a signal delay element in the feedback line. The noise resistance circuit (8) may include a filter circuit. The noise resistance circuit (8) may also include an amplifier circuit. |