http://rdf.ncbi.nlm.nih.gov/pubchem/patent/EP-0356096-A2

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Predicate Object
assignee http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_e7f89f21e647d654948da7b76556973d
classificationCPCInventive http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H03D3-00
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H03D3-248
classificationIPCInventive http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H03D3-02
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H03D3-24
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H04J1-00
filingDate 1989-08-14^^<http://www.w3.org/2001/XMLSchema#date>
inventor http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_6cdb0ece9486d9d5e77c9fef50bc09ce
publicationDate 1990-02-28^^<http://www.w3.org/2001/XMLSchema#date>
publicationNumber EP-0356096-A2
titleOfInvention Multiple reuse of an FM band
abstract A signal receiving system (10) for receiving messages from each of several unequal amplitude FM carriers (v i (t)) occupying the same portion of the frequency band. The capture effect associated with conventional frequency demodulators is utilized in a series of successively coupled phase lock loops (PLL 1 , PLL 2 , PLL 3 , ..., PLL N ) to provide demodulation of all of several FM carrier signals including weaker carrier signals in the presence of dominant carrier signals. A phase lock loop demodulator (PLL 1 ) provides a demodulated signal representing the information contained in the most dominant carrier signal input to the phase lock loop (PLL 1 ). The phase lock loop (PLL 1 also provides a replica signal (Y i (t)) which is identified to the most dominant carrier signal input. The input signal (V i (t)) is also delayed in a delay circuit (105) and input into an input port of an output circuit (106). The replica signal (Y i (t)) is also coupled to an input port of the output circuit (106). The output circuit (106) produces an output signal (Z i (t)) which is identical to the input signal (V i (t)) except that the most dominant carrier signal is suppressed. The output signal (Z i (t)) is then coupled to a successive phase lock loop (PLL 2 ) and delay circuit (115).
isCitedBy http://rdf.ncbi.nlm.nih.gov/pubchem/patent/EP-1876705-A3
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-7778365-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-7822154-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-7920643-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/EP-1335512-A3
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/EP-1335512-A2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/WO-02089371-A1
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-8208526-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/EP-1361686-A1
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-7738587-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-8259641-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-7706466-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-8005035-B2
priorityDate 1988-08-16^^<http://www.w3.org/2001/XMLSchema#date>
type http://data.epo.org/linked-data/def/patent/Publication

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isDiscussedBy http://rdf.ncbi.nlm.nih.gov/pubchem/substance/SID128500218
http://rdf.ncbi.nlm.nih.gov/pubchem/compound/CID6433

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