http://rdf.ncbi.nlm.nih.gov/pubchem/patent/EP-0860782-A1
Outgoing Links
| Predicate | Object |
|---|---|
| assignee | http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_f4964ada6006caac1715f7f32f5df380 |
| classificationCPCAdditional | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F11-104 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H04L69-324 |
| classificationCPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F11-2215 |
| classificationIPCAdditional | http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G06F11-10 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H04L29-08 |
| classificationIPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H04L29-06 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G06F13-38 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G06F11-267 |
| filingDate | 1998-02-12^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor | http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_435d14e8432d1d41234b379bd82f05ea http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_4ea4f561463bf791e8921964520e08e7 |
| publicationDate | 1998-08-26^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber | EP-0860782-A1 |
| titleOfInvention | Method of initialisation of a serial link between two integrated circuits having a parallel/serial port and device using such method |
| abstract | The present invention relates to a method for initializing anserial link between two integrated circuits with a serial parallel port andnthe device allowing the implementation of the method.n n n réinitialisation du port avec isolement de la logique d'horloge denréception ; réinitialisation de la logique d'horloge de transmission (CKT) ; remise à zéro du lien série entre les deux ports. processus bouclé, automatique ou sous la dépendance d'unnmicroprocesseur de la mise en service d'une liaison série bidirectionnelle n The method for initializing a serial link between two integrated circuits comprising an input-output port between a parallel bus and a serial link; said port using two clocks of different frequencies, a first, of higher frequency for the serial link and called transmission clock (CKT), a second, of lower frequency for the signals arriving from the parallel bus and called system clock (CKT) , is characterized in that it comprises the following stages: port reset with isolation of the receiving clock logic; reset the transmission clock logic (CKT); reset the serial link between the two ports. process complete, automatic or dependent on a microprocessor for the commissioning of a bidirectional serial link |
| isCitedBy | http://rdf.ncbi.nlm.nih.gov/pubchem/patent/AU-2008328228-B2 http://rdf.ncbi.nlm.nih.gov/pubchem/patent/FR-2979442-A1 http://rdf.ncbi.nlm.nih.gov/pubchem/patent/EP-2565810-A1 |
| priorityDate | 1997-02-19^^<http://www.w3.org/2001/XMLSchema#date> |
| type | http://data.epo.org/linked-data/def/patent/Publication |
Incoming Links
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