| Predicate |
Object |
| assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_fbb477cab6287ad715ceb612f63441ba |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G01R31-318516
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H03K19-17728
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H03K19-17736
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H03K19-17704
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G01R31-2884
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H03K19-177
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G01R31-318519 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H03K19-173
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H03K19-177
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H03K19-00
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G01R31-3185
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G01R31-28
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-82 |
| filingDate |
1995-05-18^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_dc1c5cb6a4a1dca59e20a0c9872cdb89
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_b39c4b0d02b21c4b83dacd165a88242a
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_7f3b5f3657b9637b92d31a4a65f79338
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_6a5105059b54a8821b886606e0fd2410
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_55e48205c1fd32cc303550546b350e25 |
| publicationDate |
1999-01-07^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
EP-0889593-A1 |
| titleOfInvention |
Programmable logic module for field programmable gate array device |
| abstract |
A user-programmable gate array architecture includes an array of logic functionnmodules which may comprise one or more combinatorial and/or sequential logicncircuits. An interconnect architecture comprising a plurality of horizontal and verticalngeneral interconnect channels, each including a plurality of interconnect conductorsnsome of which may be segmented, is imposed on the array. Individual ones of theninterconnect conductors are connectable to each other and to the inputs and outputs ofnthe logic function modules by user-programmable interconnect elements. A localninterconnect architecture comprising local interconnect channels is also imposed onnthe array. Each local interconnect channel includes a plurality of local interconnectnconductors and runs between pairs of adjacent ones of the logic function modules. |
| isCitedBy |
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-6765427-B1
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-6980027-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-6772387-B1
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-7389487-B1
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-6774667-B1
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-6825690-B1
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-6750674-B1
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-6799240-B1
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-6727726-B1
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-6549035-B1
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-6794897-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-7774665-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-6038627-A
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-8990757-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-7124347-B2 |
| priorityDate |
1994-05-19^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |