http://rdf.ncbi.nlm.nih.gov/pubchem/patent/EP-1020868-A1

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filingDate 1997-02-17^^<http://www.w3.org/2001/XMLSchema#date>
inventor http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_cfdefdc0c2992b3859477512a3c371f1
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_fea8d9caf51b06e815b1f1790b70e378
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publicationDate 2000-07-19^^<http://www.w3.org/2001/XMLSchema#date>
publicationNumber EP-1020868-A1
titleOfInvention Semiconductor integrated circuit device
abstract A memory macro (MM) is a combination of functional modules such as a main amplifier module (13), memory bank modules (11) of which each memory bank operates independently, a power source circuit (14), etc. The storage capacity of the memory macro (MM) can be easily changed from a large capacity to a small one by changing the number of the memory bank modules (11). A control circuit (BKCONTH) in the memory bank modules (11) of the memory macro (MM) has an additional address comparing function (COMP). Therefore, the same page can be accessed at high speed without providing any control circuit outside the memory macro (MM). In addition, a module (17) having a function such as a memory access sequence control is provided and, when memory access is made, identification information (ID) is issued at the time of inputting/outputting address or data. Therefore, high-speed memory access can be realized by checking the coincidence between the data and address with the ID and controlling the memory access sequence so that the address inputting order and data outputting order can be changed. <IMAGE>
isCitedBy http://rdf.ncbi.nlm.nih.gov/pubchem/patent/FR-2820874-A1
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/EP-1497733-A1
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http://rdf.ncbi.nlm.nih.gov/pubchem/patent/EP-1199723-A1
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/WO-03091883-A1
priorityDate 1997-02-17^^<http://www.w3.org/2001/XMLSchema#date>
type http://data.epo.org/linked-data/def/patent/Publication

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