| Predicate |
Object |
| assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_73ebc284a55d5daf0e209d6186c9e65c |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C16-10
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C16-16
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C16-0433
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10B41-35
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10B41-30
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10B41-00 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-8247
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-788
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-792
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C16-04
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C16-10
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C16-16
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L27-115 |
| filingDate |
1997-06-13^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_b9bc7c26b088d16a4055697e1a2fc9db
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_aa00931adfea0b9ca42a2badbd2bb75d
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_a42c8fc17b2ef25be824a006ed61425d
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_b6637ad17607617df38d5ce84d796446 |
| publicationDate |
2000-07-26^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
EP-1022780-A2 |
| titleOfInvention |
Method of forming a flash memory cell |
| abstract |
A method of forming a flash memory cell including a storage transistor and an access transistorncomprises providing a tunnel oxide layer (801) on a substrate; depositing and patterning anfloating gate (803) on said first oxide layer; providing a dielectric layer (804) over said floatingngate; removing said dielectric layer except for the portion of said dielectric layer located over saidnfloating gate; forming a gate oxide layer over a portion of said substrate exposed by the previousnstep (d); and depositing and patterning a conductive layer to form a control gate (805) for saidnstorage transistor over the dielectric layer (804), and a gate (805A) for said access transistornover the gate oxide layer. |
| isCitedBy |
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-8320191-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-9030877-B2 |
| priorityDate |
1996-09-27^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |