| Predicate |
Object |
| assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_283357e4e5b1d2334bd15817360ddd5a |
| classificationCPCAdditional |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H04L7-0337
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H04L7-0054 |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H04L7-0045
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H04L7-0012
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H04L7-02
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H04L7-0337
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F13-423
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F1-12
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H03L7-085 |
| classificationIPCAdditional |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H04L7-033 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H04L7-02
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H04L7-00
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H04L7-04
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G06F1-10
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G06F13-42 |
| filingDate |
1998-10-09^^<http://www.w3.org/2001/XMLSchema#date> |
| grantDate |
2003-02-05^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_f377c87220b02f28733eff364d03f867
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_111693be48adc154e3c105756a236d2e
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_c13605c0719230543243bda648b0fbf1
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_cc02ba079601ec76d4cdd049721148a8
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_5949de3297231c562b83c46b747b8632
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_ecd64869f090d43a161f97b3c40acaac
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_27f0977789417168ca346358962baf54 |
| publicationDate |
2003-02-05^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
EP-1031093-B1 |
| titleOfInvention |
Method and apparatus for fail-safe resynchronization with minimum latency |
| abstract |
A method and circuit for achieving minimum latency data transfer between two mesochronous (same frequency, different phase) clock domains is disclosed. This circuit supports arbitrary phase relationships between two clock domains and is tolerant of temperature and voltage shifts after initialization while maintaining the same output data latency. In one embodiment, this circuit is used on a bus-system to re-time data from receive-domain, clocks to transmit-domain clocks. In such a system the phase relationships between these two clocks is set by the device bus location and thus is not precisely known. By supporting arbitrary phase resynchronization, this disclosure allows for theoretically infinite bus-length and thus no limitation on device count, as well as arbitrary placement of devices along the bus. This ultimately allows support of multiple latency-domains for very long buses. |
| priorityDate |
1997-10-10^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |