| abstract |
Banks (11-0 to 11-3) are arranged on a memory chipn(10), forming a matrix. A data input/output circuitn(12) is provided at one side of the memory chip (10).nA data bus (13) is provided among the banks (11-0 ton11-3) and connected to the data input/output circuitn(12). Each bank has a plurality of memory cell arraysn(CAlL, CAR), a cell-array controller (CAC), a rowndecoder (RD), column decoders (CD0, CD1), and a DQnbuffer (DQ). The cell-array controller (CAC) and thenrow decoder (RD) oppose each other. The columnndecoders (CD0, CD1) oppose the DQ buffer (DQ). LocalnDQ lines (18a) are provided between the memory cellnarrays (CAL, CAR), and global DQ liens (18b) extendnover the memory cell arrays (CAL, CAR). The local DQnlines (18a) extend at right angles to the global DQnlines (18b). |