| abstract |
The invention relates to constrained thin film transistors. In one example, an integrated circuit structure comprises a layer inducing a stress on an insulating layer above a substrate. A layer of polycrystalline channel material is on the stress inducing layer. A gate dielectric layer is on a first portion of the polycrystalline channel material. A gate electrode is on the gate dielectric layer, the gate electrode having a first side opposite a second side. A first conductive contact is adjacent to the first side of the gate electrode, the first conductive contact on a second portion of the polycrystalline channel material. A second conductive contact is adjacent to the second side of the gate electrode, the second conductive contact on a third portion of the polycrystalline channel material. |