| abstract |
The present invention relates to a computer system tolerating transient errors, comprising: - at least two processing units (50, 51) each comprising:. a microprocessor (54, 57) ,. a memory (53, 56) protected by an error detection and correction code,. a device (55, 58) for monitoring memory access, - an input / output bus (62), - a device (52) for managing processing units and inputs / outputs, - intermediate buses (60, 61) respectively connecting each processing unit to this device (52) for managing the processing units and the inputs / outputs. It also relates to a management method in such a system. |