http://rdf.ncbi.nlm.nih.gov/pubchem/patent/GB-2207785-A
Outgoing Links
| Predicate | Object |
|---|---|
| assignee | http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_23dc4590d4940567356288aee160e61f |
| classificationCPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C29-006 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C7-00 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C8-00 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C11-406 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C7-22 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C8-12 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C8-18 |
| classificationIPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C29-00 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C8-12 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C8-00 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G06F13-14 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C8-18 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G06F11-20 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C7-22 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L27-10 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G06F13-18 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C7-00 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C11-406 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G06F12-06 |
| filingDate | 1988-08-17^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor | http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_6b80eec746057f4cf40745191e0aec07 |
| publicationDate | 1989-02-08^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber | GB-2207785-A |
| titleOfInvention | Wafer scale integrated circuit memory |
| abstract | A wafer-scale integrated circuit comprises a few hundred modules 10 which can be connected into a long chain by commands sent to the modules along a transmit path set up by way of module inputs XINN, XINE, XINS, XINW from neighbouring modules and outputs thereto XOUTN, XOUTE, XOUTS, XOUTW, only one of which is enabled by one of four selection signals SELN, SELE, SELS, SELW acting both on transmit path logic 20 and on receive path logic 21 in a return path. A RAM unit 23 can be enabled by WRITE to write a block of data sent to RID via the transmit path and can be enabled by READ to read a block of data to ROD for return along the return path. The provision of SELN, etc READ and WRITE is effected by configuration logic 22 which includes a shift register and is responsive to a command mode signal CMND, on a line which runs to all modules in parallel. If, when CMND is asserted the bit currently in the transmit path is logic 0, the module is not addressed. If the bit is 1, the module is addressed and the bit is latched as a token within the XMIT path logic 20. The configuration logic then clocks the 1 bit token along its shift register until CMND goes low again. The first six stages of the shift register provide SELN, SELE, SELS, SELW, READ and WRITE respectively and the position of the token when CMND goes low determines which command is generated. The shift register has further stages for providing a signal ACR to reset an address counter in the RAM unit 23 and for toggling RPON which controls the power supply to the RAM unit 23 via a transistor switch. <IMAGE> |
| priorityDate | 1985-07-12^^<http://www.w3.org/2001/XMLSchema#date> |
| type | http://data.epo.org/linked-data/def/patent/Publication |
Incoming Links
| Predicate | Subject |
|---|---|
| isDiscussedBy | http://rdf.ncbi.nlm.nih.gov/pubchem/substance/SID420253832 http://rdf.ncbi.nlm.nih.gov/pubchem/compound/CID73742 |
Showing number of triples: 1 to 30 of 30.