http://rdf.ncbi.nlm.nih.gov/pubchem/patent/GB-2543987-A
Outgoing Links
| Predicate | Object |
|---|---|
| assignee | http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_d37147a1eebc1b4c794a203b6f0da7e5 |
| classificationCPCAdditional | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01R4-64 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H05K3-0005 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H05K3-3452 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H05K2201-10409 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01R12-51 |
| classificationCPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H05K1-0213 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H05K3-0005 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H05K1-0216 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01R4-64 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H05K1-0215 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01R4-34 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H05K1-115 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01R12-51 |
| classificationIPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H05K1-02 |
| filingDate | 2014-08-27^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor | http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_3f0480ad83902e2b56063ac7a1835cba |
| publicationDate | 2017-05-03^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber | GB-2543987-A |
| titleOfInvention | Printed circuit board and method for designing same |
| abstract | A method for designing a multi-threaded hole printed circuit board comprises the following steps: on the printed circuit board (10), orderly laying a top layer (11), an upper solder resist layer (12), a wiring layer (13), a lower solder resist layer (14) and a bottom layer (15) as well as a plurality of threaded hole forming parts penetrating through the printed circuit board (10) and bare copper regions thereof (17); laying a printed circuit board geometric outline layer and a wiring prohibited layer on the printed circuit board (10); on a location of the wiring prohibited layer and corresponding to the threaded hole forming part, laying a first circle (18) having a larger cross section than the threaded hole (16); on a location of the circuit board geometric outline layer and corresponding to the threaded hole forming part, laying a second circle having the same cross section as the threaded hole (16); laying copper foils respectively on the bare copper regions (17) to which the top layer (11), the upper solder resist layer (12), the wiring layer (13), the lower solder resist layer (14) and the bottom layer (15) correspond, and the area of the copper foil is not less than that of the bare copper region (17). |
| priorityDate | 2014-08-18^^<http://www.w3.org/2001/XMLSchema#date> |
| type | http://data.epo.org/linked-data/def/patent/Publication |
Incoming Links
Showing number of triples: 1 to 26 of 26.