http://rdf.ncbi.nlm.nih.gov/pubchem/patent/JP-2002124871-A
Outgoing Links
| Predicate | Object |
|---|---|
| assignee | http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_5d7576285d411d00c697e07270d2814a |
| classificationIPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-822 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L27-04 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H03L7-08 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H03L7-22 |
| filingDate | 2000-10-16^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor | http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_996860bd9398435221c173beea00fd25 |
| publicationDate | 2002-04-26^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber | JP-2002124871-A |
| titleOfInvention | Semiconductor device and operation method |
| abstract | (57) Abstract: A semiconductor device having a PLL function capable of appropriately suppressing phase jitter and an operation method thereof are obtained. SOLUTION: A first PLL function unit PLL (1): A second PLL function unit PLL (2): 2 connected in series to the first PLL function unit PLL (1): 1; LL function part PLL (1): Determines the phase jitter in the first: a first PLL function part PLL according to the determination result. (1) While performing the multiplication setting at 1, the second P The LL function unit PLL (2) is provided with a jitter determination circuit 3 for performing a multiplication setting in one. |
| isCitedBy | http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-7911220-B2 http://rdf.ncbi.nlm.nih.gov/pubchem/patent/JP-2005098981-A |
| priorityDate | 2000-10-16^^<http://www.w3.org/2001/XMLSchema#date> |
| type | http://data.epo.org/linked-data/def/patent/Publication |
Incoming Links
Showing number of triples: 1 to 37 of 37.