http://rdf.ncbi.nlm.nih.gov/pubchem/patent/JP-2004200926-A

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assignee http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_e5db580deca7130dbe51805c6c608b35
classificationIPCInventive http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H03M1-38
filingDate 2002-12-17^^<http://www.w3.org/2001/XMLSchema#date>
inventor http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_1bcfe0479cf27128ad218024a6880485
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_907b3c05e3daeb58c6257a2bd41d5559
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_cad16e59fd4de533a3bac38ae149894d
publicationDate 2004-07-15^^<http://www.w3.org/2001/XMLSchema#date>
publicationNumber JP-2004200926-A
titleOfInvention AD converter
abstract An object of the present invention is to enable high speed AD conversion by a successive approximation type AD converter. A reset circuit (6) is provided at an output terminal of an inverter (1), and a reset circuit (6) is activated only for a reset period (RT) in each bit comparison to reduce the output resistance of the inverter (1), that is, reduce the amplification factor of the inverter (1). In the remaining period of each bit comparison period, the reset circuit 6 is deactivated to increase the amplification factor of the inverter 1 so as to obtain a comparison result. The potential V N2 of the node N2 is charged and discharged by the reset circuit 6, so that the time required for changing the potential V N2 of the node N2 can be reduced even if the load current that can be supplied by the inverter 1 is small. [Selection diagram] Fig. 1
isCitedBy http://rdf.ncbi.nlm.nih.gov/pubchem/patent/JP-2007028090-A
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/JP-2014146974-A
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http://rdf.ncbi.nlm.nih.gov/pubchem/patent/WO-2009133828-A1
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/JP-2009272687-A
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/JP-4693533-B2
priorityDate 2002-12-17^^<http://www.w3.org/2001/XMLSchema#date>
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