| Predicate |
Object |
| assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_fd83260a96356882b5f50dd097411a72 |
| classificationCPCAdditional |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H03K2005-00032
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H03K2005-00208 |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H03L7-0812
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H03K5-133
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H03L7-087 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H03K5-00
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H03L7-08
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H03K5-13
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H03L7-081
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G06F1-06 |
| filingDate |
2007-12-20^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_909848dab1246d02ad69da73311ebf56 |
| publicationDate |
2009-07-09^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
JP-2009152866-A |
| titleOfInvention |
Delay control circuit and delay control method |
| abstract |
A configuration capable of eliminating a stationary phase error in a delay control circuit is provided. In a delay control circuit including a first variable delay circuit and a first phase control circuit, a second variable delay circuit disposed on one of the first and second clock paths is further provided. Using the delay value for the second variable delay circuit, additional feedback that cancels out the stationary phase error generated in the first phase adjustment circuit with respect to the first clock path or the second clock path. And a second phase adjustment circuit arranged to form a loop. [Selection] Figure 1 |
| priorityDate |
2007-12-20^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |