| Predicate |
Object |
| assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_0950e9df7f0e1b73efee1bda859951ad |
| classificationCPCAdditional |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C5-147
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C11-41
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C2207-2254 |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C29-50
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C29-028
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C11-413
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C11-417
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C29-021
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C29-02
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C29-026
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C7-02 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C11-41
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C11-413 |
| filingDate |
2008-08-25^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_b5e63d709b0c25d59a008dae77c56fd9
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_b4e5fe23abeac7cdb3cad7e6c57b89fc |
| publicationDate |
2010-03-04^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
JP-2010049770-A |
| titleOfInvention |
Semiconductor memory device and trimming method using the same |
| abstract |
Trimming of variations in threshold voltages of a plurality of memory cells collectively. The semiconductor memory device includes a memory cell formed by cross-coupling a first inverter INV1 and a second inverter INV2, a power supply terminal 21 to which a first voltage is supplied, and a second voltage. And a second voltage control unit 28 to be controlled. When reading the offset information of the memory cell 20, the voltage applied to the power supply terminal 21 and the voltage applied to the second power supply terminal 22 are equalized, and then the voltage applied to the first power supply terminal 21 is set to the first voltage. The potential applied to the second power supply terminal 22 is returned to the second potential. When stress is generated in the transistor constituting the inverter, the potential difference between the first power supply terminal 21 and the second power supply terminal 22 is set larger than the difference between the first potential and the second potential. [Selection] Figure 2 |
| isCitedBy |
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/WO-2011148898-A1
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-9368228-B2 |
| priorityDate |
2008-08-25^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |