http://rdf.ncbi.nlm.nih.gov/pubchem/patent/JP-2011160318-A

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filingDate 2010-02-03^^<http://www.w3.org/2001/XMLSchema#date>
inventor http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_7f4b33719124a0b4860bae42dabee77a
publicationDate 2011-08-18^^<http://www.w3.org/2001/XMLSchema#date>
publicationNumber JP-2011160318-A
titleOfInvention Duty correction circuit, delay locked loop circuit, column A / D converter, solid-state imaging device, and camera system
abstract A single element can handle both cases where the duty ratio is larger or smaller than 50%, and not only can the number of elements be reduced, but also the number of switching operations can be reduced, thereby reducing current consumption. A duty correction circuit, a DLL circuit, a column A / D converter, a solid-state imaging device, and a camera system are provided. A duty correction circuit includes: a C element having a first input and a second input; and an inverter connected to the second input of the C element. When both become logic “1”, the output becomes logic “1”, when both inputs become logic “0”, the output becomes logic “0”. In other states, the output retains the previous state, and C Complementary clocks having a phase difference of approximately half a cycle are input to the first input of the element 11 and the inverter 12, respectively. [Selection] Figure 3
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