http://rdf.ncbi.nlm.nih.gov/pubchem/patent/JP-2013140956-A

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filingDate 2012-12-11^^<http://www.w3.org/2001/XMLSchema#date>
inventor http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_c844da52633540fbfe9a26ddd1195131
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publicationDate 2013-07-18^^<http://www.w3.org/2001/XMLSchema#date>
publicationNumber JP-2013140956-A
titleOfInvention In-situ grown gate dielectric and field plate dielectric
abstract A method and apparatus for providing a heterostructure field effect transistor (HFET) having a high quality gate dielectric and field plate dielectric. A gate dielectric and a field plate dielectric are deposited in-situ on a semiconductor surface. The location of the gate electrode 118 may be defined by etching the first pattern in the field plate dielectric 110 and using the gate dielectric 108 as an etch stop. Alternatively, an additional etch stop layer may be deposited in-situ between the gate dielectric 108 and the field plate dielectric 110. After etching the first pattern, a conductive material may be deposited and patterned to define the gate electrode 118. A source electrode 112 and a drain electrode 114 that are in electrical contact with the semiconductor surface are formed on both sides of the gate electrode 118. [Selection] Figure 1
isCitedBy http://rdf.ncbi.nlm.nih.gov/pubchem/patent/JP-2019071497-A
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priorityDate 2011-12-12^^<http://www.w3.org/2001/XMLSchema#date>
type http://data.epo.org/linked-data/def/patent/Publication

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