http://rdf.ncbi.nlm.nih.gov/pubchem/patent/JP-2013176125-A

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filingDate 2013-04-17^^<http://www.w3.org/2001/XMLSchema#date>
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publicationDate 2013-09-05^^<http://www.w3.org/2001/XMLSchema#date>
publicationNumber JP-2013176125-A
titleOfInvention Dithering the output of a digitally controlled oscillator in a phase-locked loop
abstract An increase in power consumption is avoided by satisfying noise specifications without increasing the frequency of a PLL reference clock. A digitally controlled oscillator (DCO) 201 of a PLL 124 is dithered so that the DCO_OUT signal has a frequency that varies at dithered intervals. In one example, the DCO receives an undithered stream of incoming digital tuning words, receives a dithered reference clock signal REFD, outputs a DCO_OUT signal, and its frequency change occurs at dithered intervals. ing. When a PLL is used in the local oscillator of a cellular telephone transmitter, the new dithering of the DCO reduces the digital image noise so that the digital image noise is less at a specific frequency offset from the main local oscillator frequency. Spread frequency. [Selection] Figure 4
isCitedBy http://rdf.ncbi.nlm.nih.gov/pubchem/patent/JP-WO2017119183-A1
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