| Predicate |
Object |
| assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_e5db580deca7130dbe51805c6c608b35 |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H03L7-0807
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H04L7-0338
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H04L7-027
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H03K5-1508
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06K19-0723 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H03L7-08
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H04L7-04
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H03K5-00
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H04L7-033
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H03K5-131 |
| filingDate |
2016-10-28^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_8d8e7fbb720ca2af00d9a7e728db8837 |
| publicationDate |
2018-05-10^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
JP-2018074375-A |
| titleOfInvention |
Clock recovery circuit, semiconductor integrated circuit device, and RF tag |
| abstract |
A clock recovery circuit, a semiconductor integrated circuit device, and an RF tag capable of generating an appropriate clock from an input data signal and performing data recovery are provided. A delay line circuit for outputting a plurality of first clocks having different phases by delaying an input data signal and a register circuit for determining and writing received data in the input data signal based on the first clock. And a control logic unit 34 for controlling data writing in the register circuit based on the transition of the input data signal. [Selection] Figure 3 |
| priorityDate |
2016-10-28^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |