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filingDate 2019-01-10^^<http://www.w3.org/2001/XMLSchema#date>
inventor http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_f7880a39de5a25a7f7e773755ea36c96
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publicationDate 2019-05-23^^<http://www.w3.org/2001/XMLSchema#date>
publicationNumber JP-2019080074-A
titleOfInvention Vertical integration system
abstract Embodiments of the present invention provide an integrated circuit system. An integrated circuit system includes a first active layer fabricated on the front surface of a semiconductor die and a second prefabricated layer on the back surface of the semiconductor die, the second prefabricated The layer has electrical components embedded therein, the electronic components including at least one discrete passive component. The integrated system also includes at least one electrical pathway coupling the first active layer and the second prefabricated layer. [Selected figure] Figure 1
priorityDate 2010-12-22^^<http://www.w3.org/2001/XMLSchema#date>
type http://data.epo.org/linked-data/def/patent/Publication

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