| abstract |
A semiconductor device and a method for manufacturing the same are disclosed. The method includes a step of depositing a polysilicon gate layer on a gate dielectric formed on the surface of a substrate in a peripheral area, a step of forming a dielectric layer on the polysilicon gate layer, and a step of forming the dielectric layer on the dielectric layer. Includes a step of depositing a heightened (HE) film. Next, the HE film, the dielectric layer, the polysilicon gate layer, and the gate dielectric are patterned with respect to the high voltage field effect transistor (HVFET) gate formed in the peripheral area. High energy injection is performed to form at least one low concentration doped area within the source or drain area within the substrate adjacent to the HVFET gate. The HE film is then removed to form a low voltage (LV) logic FET on the substrate in the peripheral area. In one embodiment, the LV logic FET is a high dielectric constant metal gate logic FET. [Selection diagram] FIG. 6A |