| Predicate |
Object |
| assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_58054227722081749d7e8e121924a5c8 |
| classificationCPCAdditional |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C2029-5006
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C2029-0409
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10B61-10
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/Y02D10-00 |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C11-161
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C11-1659
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C11-15
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C11-1657
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C11-1655
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C29-50
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C29-70
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C11-1675
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F13-4027
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C29-02 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L43-08
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C13-00
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-8239
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C29-00
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C11-16 |
| filingDate |
2020-09-17^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_f51ab4e36f84f3251609af1c9b0b8e0a |
| publicationDate |
2022-03-30^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
JP-2022050059-A |
| titleOfInvention |
Magnetic storage and memory system |
| abstract |
PROBLEM TO BE SOLVED: To provide a magnetic storage device and a memory system capable of stably storing information. A magnetic storage device according to an embodiment includes a first memory cell and a control circuit. The first memory cell includes a first magnetoresistive effect element and a first switching element connected in series. In the first operation, the control circuit is configured to repeatedly apply the first voltage to the first memory cell until the first condition is satisfied. [Selection diagram] FIG. 7 |
| priorityDate |
2020-09-17^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |