http://rdf.ncbi.nlm.nih.gov/pubchem/patent/JP-H0230142-A

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assignee http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_12d24c0a12c3ecdb6d9a47d623d96e76
classificationIPCInventive http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-8249
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-761
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-76
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L27-06
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http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-331
filingDate 1988-07-20^^<http://www.w3.org/2001/XMLSchema#date>
inventor http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_03db82db1ba1a91c7f95b8b749672fb2
publicationDate 1990-01-31^^<http://www.w3.org/2001/XMLSchema#date>
publicationNumber JP-H0230142-A
titleOfInvention Manufacture of bipolar transistor for semiconductor integrated circuit device
abstract PURPOSE: To obtain a manufacturing method wherein the cost to form a bipolar transistor in a semiconductor integrated circuit device is reduced, and the time necessary for manufacturing can be shortened, by performing simultaneous heating, after a first - a third impurity whose diffusion coefficients are decreased in order are respectively introduced by ion implantation method. n CONSTITUTION: A bipolar transistor is formed in a semiconductor region 10 which is junction- isolated from a semiconductor substrate 1, of one conductivity type, provided with a buried layer 2 of the other conductivity type at a bottom part, and has the other conductivity type. In this case, first impurity P for a first semiconductor layer 11 of the other conductivity type, second impurity B, for a second semiconductor 12 of the one conductivity type, whose diffusion coefficient is smaller than the first impurity P, and third impurity A, for a third semiconductor layer 13 of the other conductivity type, whose diffusion coefficient is smaller than the second impurity B are respectively introduced into the semiconductor region 10 for a vertical type bipolar transistor, by ion implantation method. After that, each of the semiconductor layers 11-13 is subjected to simultaneous heat treatment, and thermal diffusion is so performed that the first semiconductor layer 11 only reaches the buried layer 2. For example, the above impurity P, B and A are phosphorus, boron and arsenic, respectively. n COPYRIGHT: (C)1990,JPO&Japio
isCitedBy http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-6939630-B2
priorityDate 1988-07-20^^<http://www.w3.org/2001/XMLSchema#date>
type http://data.epo.org/linked-data/def/patent/Publication

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