http://rdf.ncbi.nlm.nih.gov/pubchem/patent/JP-H0823080-A

Outgoing Links

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assignee http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_0e433c1625fc509a087c912b440da84b
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filingDate 1995-01-13^^<http://www.w3.org/2001/XMLSchema#date>
inventor http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_f775897caac05f08853712ff0ba0d98b
publicationDate 1996-01-23^^<http://www.w3.org/2001/XMLSchema#date>
publicationNumber JP-H0823080-A
titleOfInvention Method of manufacturing memory device and memory cell
abstract (57) [Summary] (Modified) [Purpose] At the design stage, it operates as a volatile memory, When the design is completed, it should be operated as a non-volatile memory. [Structure] A first antifuse A1 is provided in a memory cell, and the first antifuse A1 is operated so that the memory cell 10 can be set to a non-volatile state. The memory cell 10 has a pair of cross-connected inverters I1 and I1. 2 is provided. The first antifuse A1 is connected between the output B of one of these cross-connected inverters and ground and the first antifuse A1 is activated to set the memory cell to the first non-volatile state. The second antifuse A2 may be connected between the output B and the power supply voltage V CC and activated to set the memory cell to the second non-volatile state. These antifuses A1 and A2 Only one of the two is programmed in the memory cell.
isCitedBy http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-6625080-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-6633506-B2
priorityDate 1994-01-13^^<http://www.w3.org/2001/XMLSchema#date>
type http://data.epo.org/linked-data/def/patent/Publication

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