| abstract |
Kind Code: A1 In a PLL circuit, when the amplitude of an external clock signal becomes smaller than the amplitude of an internal clock signal, the delay time of an input buffer to which each signal is input is different, and the delay at each input buffer is different. There is a problem that a phase difference of the time difference occurs. In a PLL circuit, an internal clock amplitude conversion circuit is provided in the path of the internal clock from the internal clock to the internal input buffer, and the amplitude of the internal clock is adjusted to the amplitude of the external clock. |