http://rdf.ncbi.nlm.nih.gov/pubchem/patent/JP-H09171054-A

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classificationCPCInventive http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G01R31-318541
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classificationIPCInventive http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G01R31-3185
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G06F11-22
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filingDate 1995-12-20^^<http://www.w3.org/2001/XMLSchema#date>
inventor http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_3fb638cefe60caad45748ff857f121e3
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_7c855d60c818610cca1b691e85c1579f
publicationDate 1997-06-30^^<http://www.w3.org/2001/XMLSchema#date>
publicationNumber JP-H09171054-A
titleOfInvention Scan path configuration circuit
abstract (57) Abstract: Provided is a scan path configuration circuit capable of high-speed operation during normal operation. SOLUTION: Selectors 2 and 3 and flip-flop 4 The connection circuit CC is constituted by. The selector 2 is controlled by the test holding control signal thld, and the selector 3 is controlled by the shift mode control signal sm. The scan-in terminal si is connected to the data input 0 terminal of the selector 2. Are connected, and the flip-flop 4 is connected to the data input 1 terminal. Output terminals are connected. The output terminal of the selector 2 is connected to the data input 1 terminal of the selector 3. An input terminal d is connected to the data input 0 terminal of the selector 3. The output terminal of the selector 3 is connected to the input terminal of the flip-flop 4. The output terminal of the flip-flop 4 is a connection circuit CC Is also connected to the scan-out terminal so and the output terminal q. In normal operation, data is input using the input terminal d.
priorityDate 1995-12-20^^<http://www.w3.org/2001/XMLSchema#date>
type http://data.epo.org/linked-data/def/patent/Publication

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