http://rdf.ncbi.nlm.nih.gov/pubchem/patent/JP-S59168659-A

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http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L23-50
filingDate 1983-03-15^^<http://www.w3.org/2001/XMLSchema#date>
inventor http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_629305f71eac61e3d991cfb6cbf181e0
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publicationDate 1984-09-22^^<http://www.w3.org/2001/XMLSchema#date>
publicationNumber JP-S59168659-A
titleOfInvention Lead frame for integrated circuit
abstract PURPOSE:To contrive to enhance the characteristic and economical efficiency as a lead frame by a method wherein Pd or a Pd alloy is covered on the surface on one side or both of the chip mounting part and the wire bonding part of the lead frame. CONSTITUTION:Pd or a Pd alloy is covered on the surface on any one side or both of the chip mounting part 1 and the wire bonding part 2 of a lead frame. For example, after degreasing and activation are performed to the surface of the lead frame consisting of a Cu-0.3% Sn alloy of 0.32mum thickness, Ni plating of 0.25mum thickness is performed according to the rack plating method, and then Pd of 0.75mum thickness is plated to complete the lead frame. In addition to Pd, a Pd alloy such as a Pd-Ni alloy containing 60% or less Ni, a Pd-Co alloy containing 60% or less Co, a Pd-Ag alloy containing 70% or less Ag, a Pd-Cu alloy containing 20% or less Cu, a Pd-Au alloy containing 50% or less Au, etc. can be used, for example.
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http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-6150712-A
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http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-7285845-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/KR-100819800-B1
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/JP-2001152122-A
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-6245448-B1
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/JP-4543460-B2
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http://rdf.ncbi.nlm.nih.gov/pubchem/patent/DE-4431847-C5
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priorityDate 1983-03-15^^<http://www.w3.org/2001/XMLSchema#date>
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