http://rdf.ncbi.nlm.nih.gov/pubchem/patent/JP-S61274324-A
Outgoing Links
| Predicate | Object |
|---|---|
| assignee | http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_e5db580deca7130dbe51805c6c608b35 |
| classificationIPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-72 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-28 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-732 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-78 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-872 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-47 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-331 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-329 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-73 |
| filingDate | 1985-05-30^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor | http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_ba62a800dd9ec26820f62b96065a69fb |
| publicationDate | 1986-12-04^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber | JP-S61274324-A |
| titleOfInvention | Manufacture of semiconductor device |
| abstract | PURPOSE: To enable self alignment formation of an electrode, a wiring and an impurity doped region by introducing the impurity which was doped into a metal silicide layer and/or a seed layer into a semiconductor substrate under the metal silicide through the metal silicide after the removing process, thereby forming an impurity doped region. n CONSTITUTION: Formed on a semiconductor substrate 11 are a first insulation layer 12, a layer (seed layer) 13 becoming the seed of the selective growth of a metal silicide and being conductive, and a second insulation layer 14. After forming an opening 15 and etching the seed layer 13, a metal silicide is caused to selectively grow on the semiconductor substrate 11 under the opening 16 of the seed 13 and the first insulation layer 12 and on the side exposed in the opening 16 of the seed 13, thereby connecting the semiconductor substrate 11 and seed layer 13 by a metal silicide 17. With the second insulation layer 14 as a mask the layer 17 is etched, thereby completing an electrode or wiring consisting of the species layer 13 and the layer 17. Thereafter, an impurity-doped region 18 is formed in the semiconductor substrate 11 via heat treatment. This will enable self alignment formation of an electrode or wiring, electrode window, and impurity-doped region in the semiconductor substrate. n COPYRIGHT: (C)1986,JPO&Japio |
| isCitedBy | http://rdf.ncbi.nlm.nih.gov/pubchem/patent/WO-2014196187-A1 http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-9484342-B2 http://rdf.ncbi.nlm.nih.gov/pubchem/patent/JP-S63177555-A http://rdf.ncbi.nlm.nih.gov/pubchem/patent/JP-WO2014196187-A1 |
| priorityDate | 1985-05-30^^<http://www.w3.org/2001/XMLSchema#date> |
| type | http://data.epo.org/linked-data/def/patent/Publication |
Incoming Links
| Predicate | Subject |
|---|---|
| isDiscussedBy | http://rdf.ncbi.nlm.nih.gov/pubchem/substance/SID419578708 |
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