| abstract |
An interlayer insulating film (PIL) is formed on the semiconductor substrate (1S), and after the CMP for forming the plug (PL1) in the interlayer insulating film (PIL) is finished, the upper surface of the interlayer insulating film (PIL) is retracted. By doing so, the upper surface of the plug (PL1) is made higher than the upper surface of the interlayer insulating film (PIL). Thereby, the reliability of the vertical connection between the plug (PL1) and the wiring (W1) can be ensured. In addition, it is possible to prevent the wiring (W1) from being dug into the interlayer insulating film (PIL), or to reduce the amount dug and formed. |