http://rdf.ncbi.nlm.nih.gov/pubchem/patent/KR-100214262-B1

Outgoing Links

Predicate Object
assignee http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_526cb931f1382d6e016ee651d55e1365
classificationCPCInventive http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C8-12
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C8-18
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C11-34
classificationIPCInventive http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C11-34
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C8-12
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C8-18
filingDate 1995-10-25^^<http://www.w3.org/2001/XMLSchema#date>
grantDate 1999-08-02^^<http://www.w3.org/2001/XMLSchema#date>
inventor http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_77bad8622c1eb0c938c3e7fb6cea2b55
publicationDate 1999-08-02^^<http://www.w3.org/2001/XMLSchema#date>
publicationNumber KR-100214262-B1
titleOfInvention Memory device
abstract The memory device of the present invention is configured to drive an internal address signal to selectively drive a cell array having odd area and even area cell blocks each having at least one cell block and word lines of the odd area memory cell and even area memory cells, respectively. Inputs odd and even row decoders for decoding and external address signals of the internal address signal generator and odd and even address buffers and rasva signals for generating odd and even internal address signals, respectively. Receive a normal mode, and in a special mode, receive a rasva signal and an enable signal for a special mode, and generate an odd control signal and an even control signal for controlling the odd and even address buffers, respectively. And the external address signal input to an even address buffer. Control means for controlling the odd external address signal to be input to the odd address buffer, and the even external address signal to the even address buffer, respectively; and from the odd address buffer to select and drive the at least one cell block. And an odd-numbered and even-numbered predecoder to predecode an odd-numbered internal address signal and an even-numbered internal address signal from an even-numbered address buffer, respectively.
priorityDate 1995-10-25^^<http://www.w3.org/2001/XMLSchema#date>
type http://data.epo.org/linked-data/def/patent/Publication

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Predicate Subject
isDiscussedBy http://rdf.ncbi.nlm.nih.gov/pubchem/substance/SID453034310
http://rdf.ncbi.nlm.nih.gov/pubchem/compound/CID516892

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