| abstract |
A scalable integrated data processing device, in particular a microcomputer, comprises a processor unit comprising one or more processors and a storage unit comprising one or more memories. The data processing device is provided on a carrier substrate S, and comprises substantially parallel stacked layers P, M, MP adjacent to each other, the processing unit and the storage unit being provided with one or more layers, and The separated layer is provided with any number of processors and memories in any combination. Each layer includes a horizontal electrical conductivity structure in or on the layer that forms an internal electrical connection at that layer, each layer providing an electrical connection to another layer and an electrical connection to the outside of the data processing device. It further includes a structure. This integrated data processing device has a scalable configuration and is thus formed in principle with almost unlimited processor and memory capacity. In particular, these data processing devices form various forms of scalable parallel technology construction that are integrated with optimal interconnectivity in three dimensions. |