http://rdf.ncbi.nlm.nih.gov/pubchem/patent/KR-100496711-B1
Outgoing Links
| Predicate | Object |
|---|---|
| classificationCPCAdditional | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/B82Y40-00 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2924-0002 |
| classificationCPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-76849 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L23-53238 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-76843 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L23-5329 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L23-53228 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-76864 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-3205 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-288 |
| classificationIPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-4763 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-768 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L23-52 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/C23C18-16 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L23-532 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-28 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-288 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-3205 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-44 |
| filingDate | 2000-07-27^^<http://www.w3.org/2001/XMLSchema#date> |
| grantDate | 2005-06-23^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationDate | 2005-06-23^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber | KR-100496711-B1 |
| titleOfInvention | Reduced electromigration and stress induced migration of cu wires by surface coating |
| abstract | The idea of the present invention is to coat a 1-20 nm thick metal layer on the exposed surface of Cu conductor lines of on-chip internal interconnects (BEOL) prior to the deposition of the interlayer dielectric. This coating should be thin enough so that no additional planarization by polishing is required, whereas oxidation and surface (or adjacent) Cu diffusion (according to the inventors may be caused by metal wiring defects due to defects due to electrophoretic and thermal stresses). Protection should be provided for). In addition, the metal layer increases the adhesion between Cu and the dielectric, thus further increasing the lifetime and improving the process yield. The exposed surface is either a direct result of CMP (chemical mechanical polishing) in the damascene process or by a dry etching process in which Cu wiring is patterned. In order to reduce further processing, it is proposed that the metal cover layer be deposited by a selective process over Cu. The inventors have used electroless metal coatings such as CoWP, CoSnP and Pd to show significant reliability advantages, but chemical vapor deposition (CVD) of metals or metal forming compounds may also be used. |
| isCitedBy | http://rdf.ncbi.nlm.nih.gov/pubchem/patent/KR-100884986-B1 |
| priorityDate | 1999-07-27^^<http://www.w3.org/2001/XMLSchema#date> |
| type | http://data.epo.org/linked-data/def/patent/Publication |
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