| abstract |
A method for fabricating a vertically integrated gate-all-around multiple-nanowire channel-based non-junction transistor includes forming vertically integrated vertically integrated multi-layer nanowire channels of a plurality of nanowires; Forming an interlayer dielectric (ILD) on the vertically integrated multilayer nanowire channel; Forming holes in the interlayer insulating film such that at least a portion of the vertical integrated multilayer nanowire channel is exposed; And forming a gate dielectric layer on the interlayer dielectric layer so that the hole is filled, wherein forming the gate dielectric layer on the interlayer dielectric layer such that the hole is filled includes exposing the vertically integrated multilayer nanowire exposed through the hole, And depositing a gate dielectric film on the interlayer insulating film so as to surround at least part of the channel. |