http://rdf.ncbi.nlm.nih.gov/pubchem/patent/KR-101846991-B1
Outgoing Links
| Predicate | Object |
|---|---|
| classificationCPCAdditional | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-823814 |
| classificationCPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-785 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-7855 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-0924 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-8238 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-823807 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-66795 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-823821 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-02656 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-02532 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-823878 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-7831 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-7842 |
| classificationIPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-78 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-66 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-8238 |
| filingDate | 2016-08-11^^<http://www.w3.org/2001/XMLSchema#date> |
| grantDate | 2018-04-09^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationDate | 2018-04-09^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber | KR-101846991-B1 |
| titleOfInvention | SiGe P-CHANNEL TRI-GATE TRANSISTOR BASED ON BULK SILICON AND FABRICATION METHOD THEREOF |
| abstract | The present invention relates to a method for manufacturing a semiconductor device comprising the steps of protruding a silicon fin on a bulk silicon substrate and forming a thin silicon germanium active layer on the three sides of the silicon fin to form a well hole on three sides between the gate insulating film and the silicon pin, And the holes gathered in the respective wells move along the active layer on each side of the high mobility of the holes, so that the body biasing can be performed by the integrated structure between the silicon pin and the body as well as the ultra high-speed and low- Channel triple gate transistor that can be fabricated together with an n-channel finFET (FinFET) type transistor in the same CMOS process on one substrate, and a method of manufacturing the same. |
| priorityDate | 2016-08-11^^<http://www.w3.org/2001/XMLSchema#date> |
| type | http://data.epo.org/linked-data/def/patent/Publication |
Incoming Links
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