| Predicate |
Object |
| classificationCPCAdditional |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-41758
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-2003
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-4236
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-1066
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-0649 |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-1606
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-778
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-7783
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-24
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-0619
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-47
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-7786
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-8128
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-42316
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-402
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-0649 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-40
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-417
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-423
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-20
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-24
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-10
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-16
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-06
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-812
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-778
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-47 |
| filingDate |
2018-07-05^^<http://www.w3.org/2001/XMLSchema#date> |
| grantDate |
2021-09-24^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationDate |
2021-09-24^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
KR-102303377-B1 |
| titleOfInvention |
FET with buried gate structure |
| abstract |
FET with a buried gate structure. The gate electrode of the FET includes a plurality of buried gate structures, the upper portion of which extends over the upper surface of the substrate and the lower portion of the channel layer or the channel for the HEMT so as to contact the channel layer only from the side of the buried gate structure. buried to a depth at least equal to the depth of the 2DEG plane in the layer. A head portion that is above the upper surface of the substrate and does not contact the upper surface of the substrate contacts the top of all buried gate structures and interconnects all buried gate structures. The drain current is controlled by channel width adjustment by lateral gating of the channel layer by buried gate structures. The FET may include at least one field plate comprising a slit structure in which the field plate is divided into segments. |
| priorityDate |
2017-07-06^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |