http://rdf.ncbi.nlm.nih.gov/pubchem/patent/KR-20000011073-A
Outgoing Links
| Predicate | Object |
|---|---|
| assignee | http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_508e7d633e9f849b09bd13b1e3b5f89c |
| classificationCPCAdditional | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-0696 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/Y10S148-126 |
| classificationCPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-7813 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-7811 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-1095 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-26 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-404 |
| classificationIPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-336 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-26 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-78 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-40 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-06 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-10 |
| filingDate | 1997-05-07^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor | http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_7e99c4e070947f6988e7624ab1023439 http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_b9f8e5e7611cbc7eb8ba80f28f38932c http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_0d2514979b736bc8905212314b6959e0 http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_c645d8b60ab8d7f66004e7e3f183888c |
| publicationDate | 2000-02-25^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber | KR-20000011073-A |
| titleOfInvention | Trench transistor and manufacturing method thereof |
| abstract | The present invention relates to a trench type DMOS transistor having a deep body region 138b occupying a minimum area on the epitaxial layer 104 formed on the semiconductor substrate 100, and a method of manufacturing the same. Formed on the shir layer 104 and patterned to define a deep body region 102b, a deep body region 138b beneath it, followed by a deep body region 102b and a first oxide layer 110. Prior to forming the second oxide layer 112 to shield the remaining portion of the diffusion preventing region 105 of the first conductivity type, a deep body region 102b is formed, and then the periphery of the diffusion inhibiting region 105 is formed. A portion of the second oxide layer 112 is removed to expose the center of the diffusion barrier region 105 leaving the oxide sidewall spacer 103 in the first oxide layer 110 and the second oxide layer to shield, Next, the deep body of the second conductive form The acid is executed, resulting in a deep body region 138b in the epitaxial layer 104 between the sidewall spacers 103 and diffusion shielded by the remaining portions of the first and second oxide layers 110/112. The periphery of the forbidden region 105 is characterized by preventing the lateral diffusion of the deep body diffusion 138b without greatly limiting the diffusion depth. |
| priorityDate | 1996-05-08^^<http://www.w3.org/2001/XMLSchema#date> |
| type | http://data.epo.org/linked-data/def/patent/Publication |
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