http://rdf.ncbi.nlm.nih.gov/pubchem/patent/KR-20040028965-A
Outgoing Links
| Predicate | Object |
|---|---|
| classificationCPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-78618 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-785 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-66545 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-18 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-41733 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-42384 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-66795 |
| classificationIPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-78 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-786 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-336 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-41 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-417 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-423 |
| filingDate | 2002-09-17^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationDate | 2004-04-03^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber | KR-20040028965-A |
| titleOfInvention | Method for wrapped-gate mosfet |
| abstract | The wrapped gate transistor includes a substrate having an upper surface and first and second sides facing each other. Source and drain regions are formed in the substrate with the channel region interposed therebetween. The channel region extends from the first side to the second side of the substrate. A gate dielectric layer is formed on the substrate. The gate electrode is formed on the gate dielectric layer to cover the channel region from the top surface and the first and second side surfaces with the gate dielectric interposed therebetween. The substrate is a silicon island formed on an insulating layer of either a silicon on insulator (SOI) substrate or a conventional non-SOI substrate, and has four sides, including first and second sides. Source and drain regions are formed on portions of the substrate adjacent to the third and fourth sides perpendicular to the first and second sides. The wrapped gate structure provides better and faster potential control in the channel region, making the secondary critical slope steeper and lowering sensitivity to the “body to source” voltage. |
| priorityDate | 2001-09-21^^<http://www.w3.org/2001/XMLSchema#date> |
| type | http://data.epo.org/linked-data/def/patent/Publication |
Incoming Links
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