| Predicate |
Object |
| assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_d5d04736b0b882a4f5a1e0e0e4cd8cbb |
| classificationCPCAdditional |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L33-0066
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L33-0075
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01S5-0213
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-78
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01S5-32341
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L31-0304 |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01S5-0201
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L33-0095
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-30
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-78 |
| classificationIPCAdditional |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01S5-323 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-301
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-78
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01S5-02
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L33-00
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-86 |
| filingDate |
2004-12-02^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_888717f9b7815ecbbe60448ae8d46ac2 |
| publicationDate |
2006-09-25^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
KR-20060101528-A |
| titleOfInvention |
Semiconductor chip manufacturing method and semiconductor chip |
| abstract |
A method of manufacturing a gallium nitride compound semiconductor chip from a wafer in which a gallium nitride compound semiconductor layer is laminated on a main surface of the substrate 1 is characterized in that the first groove 11 is disposed on the gallium nitride compound semiconductor layer (2, 3) side of the wafer. ) Is linearly formed by etching in a desired chip shape, which is almost equal to the line width W1 of the first groove 11 at a position not coinciding with the center line of the first groove on the substrate 1 side of the wafer. Forming a second groove 22 having a line width W2 smaller or smaller, and separating the wafer along the first and second grooves. Thus, it allows the wafer to be accurately cut in extremely high yield, thereby increasing the number of chips obtained from one wafer and improving productivity. |
| isCitedBy |
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/KR-20200088210-A |
| priorityDate |
2003-12-05^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |