| abstract |
The DLL circuit of the present invention includes a dummy delay (dummy delay circuit 200) corresponding to an internal clock delay with respect to an external clock, a coarse delay circuit 400 and a fine delay circuit for adjusting the delay amount by a delay amount adjustment signal. A phase comparison circuit 300 for comparing a phase of a variable delay adding circuit having a 500 with an internal clock, a variable delay circuit, and a delay clock input through a dummy delay, and outputting a delay amount adjustment signal to the variable delay adding circuit. Has In the initialization mode at the start of the burst, during the one clock period of the internal clock, the first signal set to logic " 1 " is input to the variable delay adding circuit through the dummy delay, and the first delay signal is inputted by the variable delay adding circuit. The duration of logic " 1 " is detected until the end of one clock cycle of the internal clock, and the delay amount of the variable delay addition circuit is initially set by setting the delay amount of the coarse delay circuit based on the duration time. |