| abstract |
The present invention provides a shift register that can operate normally while suppressing a delay of a signal or a slowdown of a waveform. The shift register of the present invention has a plurality of stages of flip-flop circuits including a clocked inverter, and the clocked inverter includes an inverter including a first transistor and a second transistor connected in series, a third transistor connected in series, and a clocked inverter. A first compensation circuit including a fourth transistor, and a second compensation circuit including a fifth transistor and a transmission gate. By the first compensation circuit, the timing of the rising or falling of the signal output from the flip-flop circuit can be controlled in synchronization with the output of the preceding stage. In addition, the second compensation circuit may control the clock signal input. |