| abstract |
Various embodiments of methods, packaging, and circuits thereof are disclosed that include the same as those used in various power electronic applications, as well as improved power devices. One aspect of the present invention combines many charge balancing techniques with other techniques to reduce parasitic capacitance, providing other embodiments for power devices with improved voltage performance, high switching speeds and low on-resistance. will be. Another aspect of the present invention is to provide an improved termination structure for low voltage, medium voltage and high voltage devices. According to another aspect of the present invention, an improved method of manufacturing a power device is also provided. Improvements are also provided to certain process steps such as trench formation, insulating film formation in the trench, mesa structure formation, and substrate thickness reduction process. According to another aspect of the invention, a charge balanced power device is combined with temperature and current sensing devices such as diodes on the same die. Another aspect of the present invention is to improve the equivalent series resistance (ESR) of the power device through additional circuitry on the same chip as the power device, and to improve the packaging of the power device with charge balance. To provide.n n n n Power Devices, Charge Balance, Termination Structure, Super-Junction |