| Predicate |
Object |
| assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_1fad0246171945d5e4957c9be0b37a2f |
| classificationCPCAdditional |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C29-787 |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C7-24
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C29-787
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C16-22
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C17-18
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C17-14
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C29-848
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-1266
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C29-816
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-1214
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C17-165
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C8-08 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C16-08
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C16-04 |
| filingDate |
2006-12-28^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_c16431a854d76a0f86c09569daa278f8 |
| publicationDate |
2007-07-03^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
KR-20070070112-A |
| titleOfInvention |
Nonvolatile memory and its writing method, and semiconductor device |
| abstract |
Write-once memory can only write once to each memory cell; Therefore, the defective bit cannot be detected by the actual inspection of the recording. Thus, as described above, redundant circuits are provided, and no action can be taken in which the defective bit is adjusted before shipping; Therefore, it is difficult to provide a memory with almost no defects. It is an object of the present invention to provide a write once memory in which the possibility of defects is significantly reduced. A first circuit for assigning only the write-once memory to a redundant memory cell, an address to the redundant memory cell; And a second circuit for outputting a determination signal indicating whether or not writing is normally performed, and a third circuit for inputting the determination signal and controlling the first circuit and the second circuit. |
| isCitedBy |
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/KR-20120130127-A |
| priorityDate |
2005-12-28^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |