http://rdf.ncbi.nlm.nih.gov/pubchem/patent/KR-20100123149-A
Outgoing Links
| Predicate | Object |
|---|---|
| assignee | http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_c16d2144a81bfa32a665dca1e93c3d37 |
| classificationCPCAdditional | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C2213-72 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C2013-0052 |
| classificationCPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C7-12 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C13-004 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C13-0004 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C8-08 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C13-02 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C7-22 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C5-14 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C8-14 |
| classificationIPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C13-02 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C5-14 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C7-22 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C7-12 |
| filingDate | 2009-05-14^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor | http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_3cb86655f10b6f292f68d9d266073e58 |
| publicationDate | 2010-11-24^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber | KR-20100123149-A |
| titleOfInvention | Semiconductor Memory Device Using Resistor |
| abstract | A semiconductor memory device using a resistor is provided. The semiconductor memory device may include a memory cell array including a matrix of memory cells whose resistance levels change according to data stored, a plurality of bit lines, each bit line being a plurality of bit lines coupled to a column of a memory cell, and a column selection signal. Precharge the selected bit line in response to the precharge signal and a column select circuit that selects at least one bit line among the plurality of bit lines in response to the pre-signal, and apply a read bias to the precharged bit line in response to the read bias provision signal. And a read circuit configured to read data stored in the memory cell, wherein the read circuit reads the data stored in the first memory cell among the plurality of memory cells using a precharge signal having a first pulse width, and the second pulse. The second memory cell of the plurality of memory cells is formed by using a precharge signal having a width. And lead the stored data. |
| priorityDate | 2009-05-14^^<http://www.w3.org/2001/XMLSchema#date> |
| type | http://data.epo.org/linked-data/def/patent/Publication |
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