http://rdf.ncbi.nlm.nih.gov/pubchem/patent/KR-20190093905-A
Outgoing Links
| Predicate | Object |
|---|---|
| assignee | http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_86f413b91bd283efd84e5ce58f6b1bac |
| classificationCPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C11-413 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C11-412 |
| classificationIPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C11-413 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C11-412 |
| filingDate | 2018-02-02^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor | http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_5ba753034a18116d059805e8449a3f4b |
| publicationDate | 2019-08-12^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber | KR-20190093905-A |
| titleOfInvention | Sram cell for generating true random number and sram cell arry driving circuit using the same |
| abstract | The present invention relates to a technique for generating a true random number using a static noise margin (SRAM) characteristics and a read noise margin (Read Noise Margin) characteristics of the SRAM. The first aspect of the present invention is to reduce the noise margin by forming the first and second NMOS transistors constituting the latch smaller than or equal to the size of each of the first and second access NMOS transistors. According to a second aspect of the present invention, a noise margin is reduced by setting a voltage between a first node of a first inverter and a second node of a second inverter constituting a latch to an intermediate level between an internal power supply voltage and a ground voltage. |
| isCitedBy | http://rdf.ncbi.nlm.nih.gov/pubchem/patent/CN-113176872-A |
| priorityDate | 2018-02-02^^<http://www.w3.org/2001/XMLSchema#date> |
| type | http://data.epo.org/linked-data/def/patent/Publication |
Incoming Links
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