| Predicate |
Object |
| assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_70ca3ea7752cc2ae9b2687d93d702a99 |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F13-404
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F13-1673
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F9-467
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F12-1081
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F12-1045
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F13-161
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F12-0873
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F13-28 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G06F13-28
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G06F13-40
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G06F13-16
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G06F12-1045
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G06F9-46
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G06F12-0873
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G06F12-1081 |
| filingDate |
2019-07-25^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_11205381169ce65bb236972b9aaba7c0
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_91611a5e11bc289cc2926b2bc1f06c0d
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_0caa102f97b2d6106ba9b625b3e47782
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_0b48c10f2d32caa51ed326a901aea539
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_fd1ad16ef4fced97bfcc690c2a002f0e
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_ff316d69f8f63e284d25a79fd2006f0b
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_80e17f00721b6773c8d7153f4c999d3f |
| publicationDate |
2021-03-29^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
KR-20210033996-A |
| titleOfInvention |
Integrated address space for multiple hardware accelerators using dedicated low-latency links |
| abstract |
The system includes a host processor 105 coupled to a communication bus, a first hardware accelerator 135-1 communicatively linked to the host processor 105 via a communication bus, and a host processor 105 via the communication bus. It may include a second hardware accelerator 135-2 communicatively linked to. The first hardware accelerator 135-1 and the second hardware accelerator 135-2 are directly coupled through an accelerator link independent from the communication bus. The host processor 105 is configured to initiate data transmission between the first hardware accelerator 135-1 and the second hardware accelerator 135-2 directly through the accelerator link. |
| priorityDate |
2018-07-26^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |